1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit having an improved efficiency in a function test for a plurality of circuit blocks each realizing a predetermined function.
2. Description of Related Art
With a recent scale-up of a semiconductor integrated circuit, a plurality of circuit blocks for realizing various functions have been incorporated in a single semiconductor integrated circuit. These circuit blocks are interconnected to function as one semiconductor integrated circuit. On the other hand, the semiconductor integrated circuit has a plurality of input terminals and a plurality of output terminals for interface with an external of the semiconductor integrated circuit.
In addition, each of circuit blocks has a plurality of input nodes and a plurality of output nodes so that the circuit blocks are interconnected in the inside of the semiconductor integrated circuit. However, the circuit blocks cannot be controlled and observed directly at the input terminals and the output terminals of the semiconductor integrated circuit.
Nevertheless, it is necessary to verify whether or not all functions of the circuit blocks operate normally. For this purpose, it is necessary to supply a predetermined signal from the input terminals of the semiconductor integrated circuit to the respective circuit blocks and to observe the result of the operation of each circuit block at the output terminals of the semiconductor integrated circuit.
In the prior art, as a means for verifying the function of the circuit blocks, there is a means for directly connecting the input terminals and the output terminals of the semiconductor integrated circuit to the input nodes and the output nodes of any selected circuit block. However, this means requires a plurality of multiplexers and a number of interconnections, with the result that the circuit scale of the semiconductor integrated circuit inevitably becomes large.
In addition, a scan-path test is known, in which, in a test mode, all flipflops included in the semiconductor integrated circuit are cascade-connected by switching over multiplexers, so as to constitute one long shift register, and after a predetermined signal is given from the input terminal of the semiconductor integrated circuit to the shift register composed of the cascade-connected flipflops, an internal condition of the semiconductor integrated circuit is transferred into the shift register, and then, the content of the shift register is outputted to an external of the semiconductor integrated circuit. However, this means also requires a number of multiplexers for the purpose of connecting all the flipflops in the form of the shift register, and therefore, the circuit scale also inevitably becomes large.
One proposal for overcoming the above mentioned problems of the prior art is disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-08-170978 and its corresponding U.S. Pat. No. 5,729,553, the content of which is incorporated by reference in its entirety into this application. The above mentioned scan-path test is described even in JP-A-08-170978 and U.S. Pat. No. 5,729,553. In the scan-path test described even in JP-A-08-170978 and U.S. Pat. No. 5,729,553, an input signal serially supplied bit by bit from an external circuit is applied to the shift register, and the signals held in the shift register are supplied to a combinational circuit. Each of the flipflops constituting the shift register fetches the test result of the combinational circuit in a normal mode, and the test result fetched in the shift register is serially outputted bit by bit from the shift register to the external terminal in the scan mode. As a result, the test result can be observed.
Referring to FIG. 4 which shows a circuit diagram of the semiconductor integrated circuit disclosed in JP-A-08-170978 and U.S. Pat. No. 5,729,553, explanation will be made, by dividing the situation into a condition in which a function inherent to a semiconductor integrated circuit 1d is realized while exchanging various signals between an internal circuit of the semiconductor integrated circuit and an external circuit (this will be called a xe2x80x9cnormal modexe2x80x9d hereinafter), and another condition in which a function test of respective circuit blocks 81, 82 and 83 is conducted (this will be called a xe2x80x9ctest modexe2x80x9d hereinafter).
An input terminal 3 receives an input signal DIN supplied in a parallel format of for example 64 bits, from an external circuit when the semiconductor integrated circuit 1d is in the normal mode. This input signal will be called a xe2x80x9cnormal input signalxe2x80x9d hereinafter. An output terminal 7 outputs an output signal DOUT in the parallel format of for example 64 bits, to the external circuit when the semiconductor integrated circuit 1d is in the normal mode. This output signal will be called a xe2x80x9cnormal output signalxe2x80x9d hereinafter.
An input terminal 2 receives a testing input signal TIN supplied in a parallel format of for example 32 bits, from an external circuit in the test mode for the circuit block 82. In the case that the testing signal is of 64 bits, the testing input signal is given by supplying first 32 bits at a first time, and then, remaining 32 bits at a second time.
An output terminal 8 outputs a test output signal TOUT in the parallel format of for example 32 bits, to the external circuit in the test mode for the circuit block 82. This test output signal will be called a xe2x80x9ctest outputxe2x80x9d hereinafter.
An input terminal 6 receives a clock signal CLK from a circuit external to the semiconductor integrated circuit 1d. Input terminals 4 and 5 respectively receive mode control signals SEL1 and SEL2 for switching between the normal mode of the semiconductor integrated circuit 1d and the test mode of the circuit block 82. The two mode control signals SEL1 and SEL2 are required in order to perform a control of multiplexers 21 and 22 and a control of multiplexers 25 and 26, independently of each other, in the test mode of the circuit block 82.
First, the normal mode of the semiconductor integrated circuit 1d will be described. The mode control signal SEL1 is set to select output signals S71 and S72 of the circuit block 81, and the mode control signal SEL2 is set to select output signals S76 and S77 of the circuit block 82. The normal input signal DIN of 64 bits given to the input terminal 3 from the external circuit is supplied to the circuit block 81. A first 32-bit portion input of the 64-bit normal input signal thus supplied is selected as the output signal S71 of the circuit block 81 by the multiplexer 21, and then, supplied as a selected output signal S73 to a flipflop 23 so that it is stored in the flipflop 23 in synchronism with the clock CLK. The first 32-bit portion input stored in the flipflop 23 is supplied as an output signal S75 to the circuit block 82 in synchronism with the clock CLK.
The remaining second 32-bit portion input of the 64-bit normal input signal is selected as the output signal S72 of the circuit block 81 by the multiplexer 22, and then, supplied as a selected output signal S74 to a flipflop 24 so that it is stored in the flipflop 24 in synchronism with the clock CLK. The second 32-bit portion input signal S74 stored in the flipflop 24 is supplied to the circuit block 82 in synchronism with the clock CLK. An output signal S77 of the circuit block 82 corresponding to the second 32-bit portion input signal S74 is supplied through the multiplexer 26 to the circuit block 83.
On the other hand, an output signal S76 of the circuit block 82 corresponding to the first 32-bit portion input is supplied through the multiplexer 25 to the circuit block 83. The result of the operation of the circuit block 83 is outputted to the output terminal 7 as the 64-bit output signal DOUT.
Next, the test mode of the circuit block 82 will be described. In the test mode, first, the mode control signals are set to supply the testing input signal TIN to the circuit block 82. Namely, the mode control signal SEL1l is set to select an output signal S78 of the multiplexer 25 and an output signal S79 of the multiplexer 26, and the mode control signal SEL2 is set to select the testing input signal TIN and the output signal S75 of the flipflop 23.
In a first clock cycle of the clock signal CLK, the first 32-bit portion input of the testing input signal TIN given through the input terminal 2 is selected by the multiplexer 25, and the output signal S78 of the multiplexer 25 is selected by the multiplexer 21 so that it is stored in the flipflop 23.
In a second clock cycle of the clock signal CLK, the portion testing input signal TIN stored in the flipflop 23 in the first clock cycle is selected by the multiplexer 26, and the output signal S79 of the multiplexer 26 is selected by the multiplexer 22 to be supplied to the flipflop 24.
The second 32-bit portion input of testing input signal TIN given through the input terminal 2 in the same second clock cycle is selected by the multiplexer 25, and the output signal S78 of the multiplexer 25 is selected by the multiplexer 21 so that it is stored in the flipflop 23 and then supplied to the circuit block 82.
Namely, the input signal TIN is divided into the first 32-bit portion input and the second 32-bit portion input, which are supplied to the input terminal 2 in the named order, so that these portions are inputted into the circuit block 82 through different paths, respectively.
After the testing input has been supplied to the circuit block 82, the setting of the mode control signals is changed in order to observe the test result. Namely, the mode control signal SEL1 is set to select the output signal S78 of the multiplexer 25 and the output signal S79 of the multiplexer 26, and the mode control signal SEL2 is set to select the output signals S76 and S77 of the circuit block 82.
The output signal S76 indicative of the test result of the circuit block 82 corresponding to the second 32-bit portion input is supplied through the multiplexer 25 and the multiplexer 21 and stored in the flipflop 23 during the period of one clock cycle. The output signal S77 indicative of the test result of the circuit block 82 corresponding to the first 32-bit portion input is supplied through the multiplexer 26 and the multiplexer 22 and stored in the flipflop 24 during the period of the same one clock cycle.
Thereafter, the mode control signal SEL1 is set to select an output signal S78 of the multiplexer 25 and an output signal S79 of the multiplexer 26, and the mode control signal SEL2 is set to select the testing input signal TIN and the output signal S75 of the flipflop 23, again, so that the result of the test of the circuit block 82 stored in the flipflops 23 and 24 is shifted in the flipflops 23 and 24 cascade-connected in the form of a shift register.
Namely, in a first clock cycle, the test result of the circuit block 82 stored in the flipflop 24 corresponding to the first 32-bit portion input is observed at the test output terminal 8, and in a second clock cycle, the test result of the circuit block 82 stored in the flipflop 23 corresponding to the second 32-bit portion input is selected as the output signal of the flipflop 23 by the multiplexer 26 and then selected by the multiplexer 22 to be stored in the flipflop 24, and the output of the flipflop is observed as the test result TOUT at the test output terminal 8.
Namely, five clock cycles are required in order to supply the testing input signal TIN through the test input terminal 2, to cause an internal circuit of the circuit block to operate, and to observe the test result TOUT at the test output terminal 8.
Various problems have been encountered in the above mentioned prior art semiconductor integrated circuit 1d. 
A first problem is that, in the normal mode, since the flipflops exist in the input path from the circuit block 81 to the circuit block 82, the inputting of the signal from the circuit block 81 to the circuit block 82 can be performed only at a timing in synchronism with the clock, and therefore, the operation speed of the normal mode is low.
A second problem is that, in the normal mode, since the multiplexers exist in the output path from the circuit block 82 to the circuit block 83, a delay occurs in the outputting from the circuit block 82 to the circuit block 83, and therefore, the operation speed is low.
A third problem is that, in the test mode of the circuit block 82, since a plurality of multiplexers exists between the flipflops cascadexe2x80x94connected to constitute the shift register, a delay occurs in the path constituting the shift register, and therefore, the operation speed is low.
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a semiconductor integrated circuit capable of efficiently performing all function tests of a plurality of circuit blocks each realizing a predetermined function, and capable of minimizing the lowering of the circuit operation speed both in the normal mode and in the test mode.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor integrated circuit comprising a first circuit block constituting an input circuit, a second circuit block constituted of a predetermined function block, a third circuit block constituting an output circuit, the first, second and third circuit blocks being cascade-connected, and a testing additional means for performing a function test for the second circuit block, the testing additional means being provided only at an input side of the second circuit block, and the second circuit block being connected directly to the third circuit block through only interconnections.
In a normal operation mode, only one signal selection means for selecting an input signal is provided in a signal transfer path between a first output node of the first circuit block and a first input node of the second circuit block, and only one signal selection means for selecting an input signal is provided in a signal transfer path between a second output node of the first circuit block and a second input node of the second circuit block. In a testing mode using the testing additional circuit, a plurality of flipflops of the number corresponding to the number of the input nodes of the second circuit block, provided for storing a testing signal when a testing signal is applied to the second circuit block and also for storing a test result signal when the test result signal is outputted from the second circuit block, are cascade-connected to constitute a shift register, so that the test result signal is serially outputted by a shifting action of the shift register, with only one signal selection means being interposed between each pair of adjacent flipflops of the shift register.
In one embodiment of the semiconductor integrated circuit, the testing additional means includes a test input terminal for serially receiving the testing signal from an external circuit for the function test of the second circuit block, a test output terminal for serially outputting the test result signal so that the result of the function test of the second circuit block is observed externally, a clock terminal for receiving a clock signal from the external circuit, a first mode control terminal for receiving a first mode control signal from the external circuit, a second mode control terminal for receiving a second mode control signal from the external circuit, the first and second mode control signals being used for changing an operation condition in the test mode, a first multiplexer controlled by the first mode control signal for selectively outputting either a signal from the first output node of the second circuit block or a signal from the test input terminal, a first flipflop for holding the signal selected by the first multiplexer in synchronism with the clock signal, a second multiplexer controlled by the second mode control signal for selectively outputting either a signal from one of outputs of the first flipflop or a signal from the first output node of the first circuit block, a third multiplexer controlled by the first mode control signal for selectively outputting either a signal from the other output of the first flipflop or a signal from the second output node of the second circuit block, a second flipflop for holding the signal selected by the second multiplexer in synchronism with the clock signal, for outputting the selected signal to the test output terminal, and a fourth multiplexer controlled by the second mode control signal for selectively outputting either a signal from one of outputs of the second flipflop or a signal from the second output node of the first circuit block.
Furthermore, when the function test of the second circuit block is conducted, the testing additional means cascade-connects the first multiplexer, the first flipflop, the second multiplexer and the second flipflop in the named order to cause them to constitute one shift register, so that a first testing signal inputted from the test input terminal at a first clock and a second testing signal inputted from the test input terminal at a second clock are serially inputted to the shift register and held in the shift register, and the second testing signal held in the first flipflop at the second clock is supplied through the second multiplexer to the first input node of the second circuit block, and the first testing signal held in the second flipflop at the second clock is supplied through the fourth multiplexer to the second input node of the second circuit block, and wherein, of the test result of the function test of the second circuit block, a first partial output is held in the first flipflop through the first multiplexer at a third clock, and simultaneously, a second partial output is held in the second flipflop through the third multiplexer, and thereafter, the first flipflop and the second flipflop are cascade-connected to constitute the shift register, again, under control of the first mode control signal, the test result of the function test is serially outputted from the test output terminal at fourth and fifth clocks.
In one modification of the semiconductor integrated circuit, the number of the input nodes of the second circuit block is larger than the number of the output nodes of the second circuit block by at least one, and the first circuit block includes a third output node, and the second circuit block includes a third input node. The testing additional means further includes a fifth multiplexer controlled by the first mode control signal for selectively outputting either a signal from the other output of the second flipflop or the signal from the second output node of the second circuit block, a third flipflop for holding the signal selected by the fifth multiplexer in synchronism with the clock signal, for outputting the selected signal to the test output terminal, and a sixth multiplexer controlled by the second mode control signal for selectively outputting either a signal from one of outputs of the third flipflop or a signal from the third output node of the first circuit block, the third multiplexer receiving the signal from the first output node of the second circuit block in place of the signal from the second output node of the second circuit block, so that the number of the input nodes of the second circuit block is adapted to the number of the output nodes of the second circuit block.
In another modification of the semiconductor integrated circuit, the number of the output nodes of the second circuit block is larger than the number of the input nodes of the second circuit block by at least one, and the second circuit block includes a third output node. The testing additional means further includes an exclusive-OR circuit of the number smaller than the number of the input nodes of the second circuit block by at least one, and the third multiplexer other than the first multiplexer, of the multiplexers located at an input side of the first and second flipflops, receives, in place of the signal from the second output node of the second circuit block, an output signal of the exclusive-OR circuit receiving signals which are outputted from the second and third output nodes of the second circuit block, so that the number off the output nodes of the second circuit block is adapted to the number of the input nodes of the second circuit block.
Furthermore, each of the input signal given to the first circuit block and the testing signal given to the testing additional means is a signal of an arbitrary bit number, and each of the output nodes of the first circuit block and the input nodes of the second circuit block is a signal of the same arbitrary bit number obtained by dividing the arbitrary bit number, and each of the output nodes of the second circuit block is a signal of the bit number including the same arbitrary bit number and obtained by dividing the arbitrary bit number.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.